The Challenge
Field Programmable Gate Arrays (FPGAs) are rapidly becoming a common platform for providing specific high-speed processing for DoD applications. The re-programmable nature and high performance capabilities (versus traditional embedded processors) of this customizable technology make it desirable for real-time processing during prototype development without the long fabrication time required for custom circuitries.
Our Approach
The problem however, is that the design cycle for a typical FPGA development is very time-consuming and convoluted in nature. Many complexities exist in a typical FPGA design flow, including:
- A design cycle that involves several engineers with different expertise.
- And a multiple iterations of CAD tool manipulations through configuration of the design options.
These complexities stem from both the various CAD tools required in the multiple steps within the FPGA design flow and the multitude of design options specific to each tool. Understanding these design options and their potential effect on a design for each step within the design flow process requires years of experience in disparate disciplines, resulting in the need for several engineers to be involved in the process and several design iterations. This project examines the complexities that exist in a typical FPGA design flow and the need to simplify the process through a unifying interface and intelligent design optimization to enable even a single engineer without design experience to create an effective design.
The F-PAS (Field-Programmable Automation System) application is a system that simplifies the FPGA design flow while intelligently producing the best implementation solution. By utilizing an intelligent automation system, the F-PAS application simulates the design process of experts and leverages expertise gained only by experience. This intelligent automation feature provides the flexibility to implement Verilog or C designs with the option of manually configuring some tool options to utilize an expert designer’s time and effort more effectively or even allow a single novice engineer to complete an implementation, increasing productivity in FPGA design while producing the most effective design solutions for the specific application.
In a small scale study, F-PAS achieved lower power than standard tool optimization within 20 iterations for 18 out of 22 projects (81.8%) without any manual configuration or supervision. It achieved greater speed than standard tool optimization within 20 iterations for 16 out of the 22 projects (72.7%) and an average speed increase of 8.34%.
